Hardware Optimized Sample Rate Conversion for Software Defined Radio

The evolution towards applications with increasing functionalities leads to the need of high flexible systems that support a high number of different standards while decreasing the required hardware space. Therefore a high configurable platform being able to handle a multitude of standards is needed. One main issue is the tradeoff between performance and space consumption. We present a generic, flexible, fractional and hardware optimized SRC architecture in the context of SDR, providing one architecture to process up to 8 different complex channels. The solution is based on bandlimited interpolation and allows processing by supporting a 1Hz resolution of the sampling rates. Index Terms – SDR, SRC, Hardware Architecture, Open Platforms for Multistandard Support, Baseband Processing, HW Accelerators